Reproducible TRNG Integration in a RISC-V SoC

This master’s thesis was developed in the context of the VE-HEP (Versatile Hardware Execution Platform) project, a research initiative aimed at building a flexible and secure RISC-V-based SoC. The core contribution is the integration of a physical True Random Number Generator (TRNG) — designed following the OpenTRNG open-source framework — directly into the SoC’s peripheral bus.

The TRNG IP is exposed to the processor via an APB3 wrapper written in SpinalHDL, with a well-defined register map that allows firmware to configure the entropy source, read raw samples, and monitor health-test status. A lightweight C firmware driver was implemented to exercise the peripheral and validated end-to-end through functional simulation. The hardware description was also cross-verified at the Verilog netlist level to ensure correctness after synthesis.

A key focus of the thesis is reproducibility: the entire toolchain — SpinalHDL compiler, Verilator simulation, synthesis scripts, and firmware compilation — is packaged as Nix derivations managed through a Nix Flake. This guarantees that any developer can reproduce the exact same build environment with a single nix develop invocation, eliminating dependency drift and making the project suitable for long-term archival and peer review.