Reproducible TRNG Integration in a RISC-V SoC

Fri, 27 Mar 2026 00:00:00 +0200

This master’s thesis was developed in the context of the VE-HEP (Versatile Hardware Execution Platform) project, a research initiative aimed at building a flexible and secure RISC-V-based SoC. The core contribution is the integration of a physical True Random Number Generator (TRNG) — designed following the OpenTRNG open-source framework — directly into the SoC’s peripheral bus.

The TRNG IP is exposed to the processor via an APB3 wrapper written in SpinalHDL, with a well-defined register map that allows firmware to configure the entropy source, read raw samples, and monitor health-test status. A lightweight C firmware driver was implemented to exercise the peripheral and validated end-to-end through functional simulation. The hardware description was also cross-verified at the Verilog netlist level to ensure correctness after synthesis.

SpinalHDL on Giovanni Nicosia

Reproducible TRNG Integration in a RISC-V SoC